The design of most digital ICs is today a highly structured process based on a hardware description language (HDL) methodology. In an HDL method, the IC to be designed is first specified by a specification document. Then, the IC design is reduced to HDL code. This level of design abstraction is referred to as the register transfer level (RTL), and is typically implemented using an HDL language such as Verilog or VHDL. At the RTL abstraction, the IC design is specified by describing, in HDL code, the operations that are performed on data as it flows between circuit inputs, outputs, and clocked registers. The RTL description is referred to as the RTL code. The IC design, as expressed by the RTL code, is then synthesized to generate a gate-level description, or a netlist. The step of translating the architectural and functional descriptions of the design, represented by RTL code, to a lower level of representation of the design such as logic-level and gate-level descriptions is referred to as synthesis.
The IC design specification and the RTL code are technology independent. That is, the specification and the RTL code do not specify the exact gates or logic devices to be used to implement the design. However, the gate-level description of the IC design is generally technology dependent. This means that at this level the design is targeted to a specific manufacturing process. Generally, the design and manufacture of ICs is an expensive process. The expenses increase significantly towards the later stages of the design and manufacturing process. It is therefore necessary to provide tools that are capable of assisting the IC designer to detect design faults, also known as design “bugs”, as early as possible in the design process. One such method is described in U.S. patent application Ser. No. 10/118,242, entitled “An Apparatus and Method for Handling of Multi-Level Circuit Design Data”, assigned to the assignees of the present application, and hereby incorporated by reference in its entirety.
In many instances it is useful to be able to recognize a certain type of pattern in a logic design description. Recognizing these patterns then allows more detailed analysis around them. Referring to FIG. 1, a portion of a circuit 100 containing a data synchronizer 110 is shown. The synchronizer is a structure used to ensure that data is faithfully passed between two asynchronous clock domains. The two clock domains represent two portions of a circuit that are capable of functioning independently, including but not limited to operating within different frequencies of operation, but which still need to maintain the capability of transferring data from one circuit to the other.
Though many techniques for implementing such a structure are known, most designers practically use only a few techniques. Mostly the techniques that are used are the ones that the designer has determined to be acceptable for a specific objective. Therefore, it would then be desirable to be able to check, as part of the verification process, that every instance of synchronization in the design uses only an approved technique.
Such a verification task, if done manually using visual aids, would of course be impractical for today's sophisticated ICs containing millions of transistors. In performing such verification at the RTL level, recognizing patterns from an RTL description is extremely complex. This is because circuits may be represented in functionally equivalent but syntactically different ways. It is further possible that some portion of the circuit may straddle hierarchy boundaries, or have other characteristics that make identification very difficult from the syntax description. Referring again to FIG. 1, the RTL representation of the synchronizer might appear (in Verilog) as:
always @(posedge CLK2) beginif ( sel ) sel_in <= ready;else sel <= sel_in;endor,always @(posedge CLK2) beginif ( sel ) out <= in;else out <= out;end
It should be noted that the above two examples are only a couple of the numerous ways that the same functionality could be shown using the syntax available for RTL description.